1. Field of the Invention
The present invention relates to a delay circuit. More specifically, the present invention relates to a delay circuit utilizing a memory and capable of varying a delayed time.
2. Description of the Prior Art
By A/D converting an input analog signal to be written in a memory and by reading the signal being stored in the memory to be D/A converted, it is possible to obtain a delay circuit having a delay time from the writing timing to the reading timing. For example, with respect to addresses of the memory from A.sub.l address to A.sub.N address, if the writing of the signal as A/D converted and reading the same are repeated, it is possible to obtain a delay time equal to clock signals of N, and if the number of addresses being used is changed, it is possible to vary the delay time correspondingly thereto.
In such a delay circuit, if the number of addresses to be used of the memory is changed to vary the delay time in the course of the operation thereof, addresses that have not used until this time become to be newly used. In such a case, since random data are stored in the addresses which become to be newly used, there was a problem that a noise is generated on the output if the random data are read and used as they are.